Single-atom nanoelectronics

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Feb 20, I had a hard time listening after he said a nanometer was one trillionth of a millimeter. Report Block. Switching states and the ability to create different devices on the fly is amazing. Another 20 years and we'll be able to build our own UFO.

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Your name. Note Your email address is used only to let the recipient know who sent the email. Figure 8 shows the change in current-voltage characteristic before and after the selective burning of metallic CNT. The inset chart in this figure demonstrates the curve for the rectifier for low bias voltages. Figure 9 shows the current-voltage curves of symmetric devices, i. All electrical measurements were made at room temperature in the air. The on-off ratio is about 10 4.

Nanoelectronic Devices Based on Carbon Nanotubes

As seen in Fig. In microelectronics, the basic structure of a field-effect transistor FET of solid state is composed of two metal electrodes called source and drain, which are connected by a channel in a semi-conductor. There is a third electrode, called the gate, which is isolated from the channel by a thin layer of SiO 2. By varying the channel width, the gate bias voltage controls the current flow between the source and drain terminals.

These electrodes are typically made of Au or Pt Avouris, An example of this transistor is shown in Fig. In this picture, a carbon nanotube is positioned at the top, interconnecting thus the two electrodes of noble metals. These electrodes are the source and drain terminals of the FET, which were fabricated at the top of a SiO 2 film, which, in turn, was deposited on a Si wafer.

This Si wafer operates as a third terminal, which has the function of gate. These devices have the properties of a p-type FET with the ratio of on-off current of the order of 10 5. The terminals are made of Ti or cobalt Co. The curve of Fig. The thickness of the SiO 2 under the gate is 15 nm.

Single-atom transistor

A reduction of the parasitic resistance is obtained by heat treatment between the metal and the SWCNT. The device in Fig. Currently, there are several geometric configurations that can be used in implementation of the CNFET. The most commonly used are shown in Fig. In the settings of Fig. The gate can be both top-gate and back-gate and, as a common use, all configurations make use of a dielectric or an oxide in order to isolate the gate terminal of the CNT. When a bias voltage is applied at the gate terminal of the CNFET, a perpendicular electric field appears in the channel of this device.

This electric field controls the amount of charge carriers in the channel. The control can be fulfilled in two different ways: by top-gate, when the gate terminal is placed over the CNT, or by back-gate, when the gate terminal is underneath the Si wafer, which is heavily doped. The top-gate controls the channel that is right below the gate terminal and the back-gate does the same control, but now, through an electrostatic doping in a region of the CNT near of the drain and source terminals in order to decrease the contact resistance between these terminals.

This doping is done by electrostatic application of vertical electric field that induces electrons or holes near the region of the drain source terminals. Regardless of the type of control used, whether by a top-gate or a back-gate, there is an electric field due to the applied bias between drain and source. This electric field is responsible for the displacement of charge carriers between the drain and source terminals, whose intensity is controlled by the gate terminal.

Figure 13a depicts the scheme of the device of Fig. The difference between Fig. The top-gate is separated from the CNT by a high-k dielectric the high-k dielectric has the dielectric constant k several times much greater than that of SiO 2.

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Therefore, in this geometry, one can control the current flow between source and drain terminals, both through the top-gate and by the back-gate. Figure 13c uses the chemical doping in the regions close to the source and drain terminals, and Fig. Controlled devices through the top-gate are preferred when a greater control of the channel is desired, as well as the top-gate allows the control of individual gates on a device with multiple transistors. These schemes are independent on the geometric setting.

They are defined by the length, the mean free path of the CNT and the type of contact between the terminals, i.

Physicists Create a Working Transistor From a Single Atom

In the projects of CNFET devices, one needs to optimize the current between source and drain terminals. In this sense, projects with transparent contacts i. Due to the 1-D nature of CNT, in the linear region, the electrons can move only in one direction, i. In the active regions of the MOSFET, the current of saturation is due to the pinch-off that occurs in the channel and, as a consequence, the drift rate no longer depends on the drain voltage Martel et al.

As for CNFET, the current of saturation occurs due to disappearance of the charge carriers from the drain terminal. Table 2 shows explicitly that the device current in the on state I ON for the MOSFET is controlled mainly by the drift velocity u eff , which depends on the properties of the material. Whereas for CNFET this current mainly depends on the physical properties of states of the electrons in the solid, such as the band-gap structure E g , the Boltzmann constant k s depends on the temperature T and the quantum resistance R q Wong and Akinwande, The other parameters of Table 2 have already been described in the text.

In the nanoscale simulations, one needs to consider the effects of a single atom on the characteristics of the device. In the atomic scale, the effects of the individual vacancies and impurities start to have a real influence in the performance of the device.

There are two main steps in the nanoelectronic studies. The first one is a solution of the electronic structure problem that deals with the behavior of electrons' band energy inside of the material as well the DOS in such energy levels. In practice, this study gives us the information about the band gap and the energy levels where the device will work properly. An example of such methods is density-functional theory DFT. The second category is semi-empirical methods where the electronic structure is calculated by using adjustable parameters obtained, for example, from experiments.

The second step is the study of electronic transport, i. The problem here is usually to obtain the I-V current-voltage characteristic curves. In this step, it is necessary to consider the electrons as wave functions instead of particles. That is, it is important to take into account the quantum effects that appear in the atomic scales. At these scales, the channel of the device the active region of interest is frequently shorter than the mean-free path of the material. A combination of the Landauer approach with the non-equilibrium Green function NEGF method is now widely used in the analysis and design of nanoscale devices.

Quantum transport in nanotubes and other nanoelectronic devices is described in more details in Wong and Akinwande, ; Javey and Kong, ; Stokbro et al. Some special electrical, optical and magnetic properties, the mechanical strength and chemical stability make the CNT one of the promising nanomaterials to be used in nanoelectronics. Based on the available literature, this study shows that the devices with CNT are very promising for replacing microelectronic devices that employ Si, germanium Ge or GaAs as semi-conductor elements.

The use of CNT as a metal to interconnect elements in order to replace the copper tracks is advantageous when the mean free path is smaller than the link track. I see that myself.

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Our group publishes about our devices, but practically nothing at the systems level. There's a good reason for that.

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Systems are where lots of know-how and differentiation come from. When things start to move into systems, it's like a black hole, they just disappear from sight.